1. Field of the Invention
The present invention relates to an integrated circuit structure and a method for manufacturing the same, and more particularly to a semiconductor device and a manufacturing method thereof.
2. Description of Related Art
In the field of integrated circuit devices, the dimensions of the devices are often reduced to attain a higher operating speed and a lower power consumption. However, with the ever-increasing level of integration of devices, the miniaturization of devices has almost reached its limit. Hence, other means of reducing device dimensions are required to increase the operating speed and reduce the power consumption. Therefore, how to increase the driving current and avoid forming defects in the device has long been an issue under study.
One proposed solution to overcoming the limitations imposed by device miniaturization includes controlling the strain in the channel region of a transistor. A method for strain control is utilizing materials having an identical crystal structure but different lattice constants to achieve the purpose of controlling the strain. If a transistor is an N-type transistor, implanted strain atom are carbon atom and formed into an epitaxial structure of silicon carbide (SiC). Since the lattice constant of carbon atoms is usually smaller than that of silicon atoms, if SiC is embedded in source and drain regions, a tensile stress can be generated in the channel to enhance the mobility of electrons so that the driving current of the device is increased. If a transistor is a P-type transistor, implanted strain atom are germanium and formed into an epitaxial structure of silicon germanium (SiGe). A compression stress can be generated in the channel to enhance the mobility of holes.
Currently, there is one method in which the predetermined source and drain regions are removed in the substrate by an etching process to form a trench and then a epitaxial material layer is deposited therein. However, since the solid solubility of strain atoms in silicon crystals is quite low, the concentration of a semiconductor compound solid-phase epitaxy layer formed by the strain atoms is very low. Moreover, in this method, more than half of the strain atoms are located on the interstitial sites in the crystal, instead of the substitutional sites.
Currently, the company IBM proposes a solid-phase epitaxy (SPE) process. An N-type transistor is exemplified herein. High-concentration carbon atoms are implanted into source and drain regions, and then SiC is formed therein by a solid-phase epitaxy annealing process. As pointed out by IBM, in the method, not only are more carbon atoms located on the substitutional sites, but the annealing process required by implanting the carbon atoms can also be completed altogether when SiC is epitaxy grown by a subsequent solid-phase epitaxy process. One annealing process is thereby omitted.
The manner of strain control utilized in the channel region of the transistor is related to a surface concentration of the strain atoms. Generally, strain atoms with a higher concentration on the substrate surface at the two sides of the gate structure would create a stronger strain (tensile stress or compression stress) and thereby increasing the driving current. Nevertheless, the method proposed by IBM to implant high-concentration carbon atoms at one time is very likely to cause defects on the surface of the source and drain regions and trigger leakage even though the required concentration of the SiC solid-phase epitaxy layer on the surface of the source and drain regions can be thus obtained.